The present invention generally relates to a memory system using non-volatile semiconductor memory cells, and more particularly to a non-volatile semiconductor memory system improved in a characteristic of writing data into memory cells and reduced in power consumption at the time of data write.
The non-volatile semiconductor memory system using non-volatile memory cells, for example, floating gate type MOS transistors, is known as an EPROM (Erasable Programmable Read Only Memory). In storing data into the floating gate type memory cells, a high voltage is applied to the control gate provided above the floating gate through an insulating layer and the drain of the memory cell while holding a reference voltage Vs having about ground potential applied to the source, thereby causing the impact ionization to take place between the drain and the source. Of electron-hole pairs produced by the impact ionization, electrons are captured by the floating gate to change the threshold voltage of the memory cell. According to the change of the threshold voltage, data is stored. In memory cells of this type, the substantial gate potential is changed depending on a quantity of the electrons captured by the gate. Accordingly, the data stored in the memory cell can be detected (read out) through a change in the channel current of the MOS transistor. Practically, in writing data into the memory cell, a high voltage of 20 to 25 V is usually applied to the control gate above the floating gate and the drain. In reading out data, some 5 V is applied to the control gate usually.
In the prior EPROM, the write voltage applied to the control gate is fixed at 25 V. Accordingly, 50 ms is usually taken for writing data into one memory cell. Accordingly, when data is written into all the memory cells in a 4 K words.times.8 bits, for example, about three minutes must be taken. For reducing the write time, a gate voltage applied to the control gate of each memory cell and/or a drain voltage applied to the drain must be set to be higher than those of the prior one. Practically, to realize this, a power source voltage externally supplied to the memory system, e.g. a write power source voltage, is boosted by a voltage boosting circuit. Then, the boosted voltage may be applied to the control gate of the mcmory cell or the boosted voltage is applied to the control gate and at the same time a voltage which is higher than that of the prior art one and obtained using the boosted voltage may be applied to the drain of the memory cell. Generally, the boosting circuit is constructed such that it is contained in the integrated circuit of the memory system, and a given power source voltage for feed to the memory system, e.g. a write voltage, is boosted up to a given voltage by using a capacitance coupling. With this circuit arrangement, the output current from the boosting circuit is limited to a great extent. In recent memory systems in which transistors are extremely minute, the memory capacity is much larger, and the row and column lines are greater in number, the current consumed in the decoder sections is greatly increased. In order to reduce the current consumption in the decoder sections when data is written into the memory cell array, it is accordingly necessary to apply the boosted voltage to only the selected column or row line. Nevetheless, the prior non-volatile semiconductor memory system is not so arranged that the output current of the boosting circuit is decreased by selectively applying the boosted voltage to a peripheral circuit of the memory cell array, e.g. the write circuit.
For a better understanding of the present invention, an outline of a prior non-volatile semiconductor memory system will be described referring to FIG. 1. In the Figure, R.sub.1 to R.sub.m designate row lines and D.sub.1 to D.sub.n column lines. Memory cells TM.sub.11 to TM.sub.mn each made up of a floating gate type MOS transistor are located at cross points of the row and column lines and arranged in a matrix fashion. The control gates of the memory cells TM.sub.11 to TM.sub.mn are connected to the corresponding row lines R.sub.1 to R.sub.m, respectively. Similarly, the drains are connected to the corresponding column lines D.sub.1 to D.sub.n, respectively. A reference voltage V.sub.S, e.g. an earth potential, is applied to the sources of all the memory cells TM.sub.11 to TM.sub.mn. The row lines R.sub.1 to R.sub.m, the column lines D.sub.1 to D.sub.n, and the memory cells TM.sub.11 to TM.sub.mn cooperate to form a memory cell array 10.
The row lines R.sub.1 to R.sub.m are connected to a row decoder 20, through MOS transistors TR.sub.1 to TR.sub.m of the depletion type (D type). A read/write control signal R/W is applied to the gates of the MOS transistors TR.sub.1 to TR.sub.m. The row decoder 20 responds to address signals to select one row line and to produce a high level signal at the output terminal corresponding to the selected row line.
The column lines D.sub.1 to D.sub.n are connected to a signal detection node N1, through corresponding MOS transistors of those transistors TD.sub.1 to TD.sub.n provided in the column line selection circuit 30 for selecting a column line. The signal at the node N1 is sensed by a sense amplifier 40 and the sensed signal is produced through an output circuit 50 to the outside of the memory system. Column selection lines C.sub.1 to C.sub.n are connected to the gates of the MOS transistors TD.sub.1 to TD.sub.n, respectively. The column selection lines C.sub.1 to C.sub.n are connected to a column decoder 60, through the MOS transistors TC.sub.1 to TC.sub.n correspondingly arranged. The column decoder 60 responds to selection address signals supplied to the column decoder itself to select one of the column select lines and provides a high level signal at the output terminal connected to the selected column selection line.
The other terminals of the row lines R.sub.1 to R.sub.m and the column lines C.sub.1 to C.sub.n are respectively connected to the D type MOS transistors WR.sub.1 to WR.sub.m and WC.sub.1 to WC.sub.n in a corresponding manner. The drains of those D type MOS transistors are connected to a terminal for applying the write voltage V.sub.p. The sources and gates of those D type MOS transistors are connected to the corresponding row and column lines, respectively. The MOS transistors WR.sub.1 to WR.sub.m and WC.sub.1 to WC.sub.n are all contained in a write transistor circuit 70. A write transistor T1 of the E type (enhancement type) is connected between the signal sense node N1 and the write voltage V.sub.p applying terminal. A signal on the output node N2 of the write-in data control circuit 80 is supplied to the gate of the write MOS transistor T1. The write-in data control circuit 80 is comprised of an internal data producer 85 which receives the external input data D.sub.in to produce internal data d.sub.in corresponding to the external input data D.sub.in, an inverter IN1 inserted between the voltage V.sub.p applying terminal and the reference voltage V.sub.S (ground potential), and an E type MOS transistor T4 for receiving at the gate a read/write signal R/W by being inserted between the output node N2 and the reference voltage V.sub.S (ground potential). The inverter IN1 is comprised of a D type MOS transistor T2 connected at the source-drain path between a voltage V.sub.p applying terminal and the node N2, and at the gate to the node N2, and an E type MOS transistor T3 which is connected at the source-drain path between the node N2 and the reference voltage V.sub.S and receives the internal data d.sub.in at the gate.
The operation of the memory system shown in FIG. 1 will be given. For reading out the data from the memory cell array 10, the read/write signal R/W is high ("1") in level and the write voltage V.sub.p is 5 V. For this, the MOS transistors TC.sub.1 to TC.sub.n, and TR.sub.1 to TR.sub.m are turned on, the MOS transistor T4 is also turned on, and the MOS transistor T1 is turned off. The conductance g.sub.m of each of the MOS transistors WC.sub.1 to WC.sub.n and WR.sub.1 to WR.sub.m in the write transistor circuit 70 is set at an extremely small value. Therefore, of the row lines R.sub.1 to R.sub.m and column select lines C.sub.1 to C.sub.n, only those selected by the row decoder 20 and the column decoder 60 are set at high level, while those not selected are set at low level. As a result, a memory cell located at the cross point of the selected row and column lines is driven. If no data has been written into the selected memory cell, the memory cell is turned on because at this time the threshold voltage of the selected memory cell having no data written is low. Upon turning on of the memory cell, current flows through the source-drain path, so that the signal sensing node N1 becomes low in level. On the other hand, if data has been written into the selected memory cell, the memory cell is turned off because at this time the threshold voltage of the selected memory cell having data written is high, and the node N1 becomes high in level. The high level signal at the node N1 is led out to the exterior through the sense amplifier 40 and the output circuit 50.
In a write mode, the read/write signal R/W is low and the write voltage V.sub.p is 25 V. Assume now that the row line R.sub.1 is selected by the row decoder 20 and the column select line C.sub.1 is selected by the column decoder 60. Then, the MOS transistors TR.sub.1 and TC.sub.1 are turned off. Under this condition, the row line R.sub.1 is charged up to 25 V (equal to the write voltage V.sub.p) through the MOS transistor WR.sub.1, and the column selection line C.sub.1 is charged up to 25 V through the MOS transistor WC.sub.1. The row and column lines not selected are low in level, i.e. at ground potential, since the MOS transistors TR.sub.2 to TR.sub.m and TC.sub.2 to TC.sub.n are turned on because of that the outputs of the row and column decoders corresponding to these row and column selection lines not selected. At this time, if the external input data D.sub.in is low, the internal data d.sub.in is also low and 25 V (V.sub.p) appears at the node N2. For this reason, the MOS transistor T1 is turned on and the node N1 is charged up to about 22 V given by V.sub.p -V.sub.TH where V.sub.TH is a threshold voltage of the MOS transistor T1. Accordingly, 25 V (V.sub.p) is applied to the control gate of the memory cell TM.sub.11 selected by the row line R.sub.1 and the column line D.sub.1. About 22 V given by (25-V.sub.TH(T1)) V or (25-V.sub.TH(TD1)) V is applied to the drain of the memory cell TM.sub.11, where V.sub.TH(T1) is a threshold voltage of the MOS transistor T1, and V.sub.TH(TD1) is a threshold voltage of the MOS transistor TD.sub.1. As a result, the impact ionization takes place in the memory cell TM.sub.11 and data is writen therein. If, at this time, external input data D.sub.in is high in level, the MOS transistor T1 is turned off, so that the 22 V is not applied to the drain of the memory cell TM.sub.11. Therefore, no data is loaded into the memory cell TM.sub.11. The memory cell, into which data is once loaded, keeps the data in non-volatile manner, so long as the data is not erased.
As already described, in the memory system in FIG. 1, the write voltage V.sub.p is fixed at 25 V. Therefore, a long time is needed in order to write the data into all the memory cells in the memory cell array. To solve this problem, a higher voltage than that of the prior art must be applied to the control gates of the memory cells or to both the control gates and the drains. The reason for this will be given referring to FIGS. 2A to 2C. FIG. 2A illustrates a symbolic representation of the floating gate type MOS transistor. V.sub.D designates a drain voltage and V.sub.G a voltage applied to the control gate. FIG. 2b shows a relationship between a control gate voltage V.sub.G and a change .DELTA.V.sub.TH of the threshold voltage of the memory cell when the data write is performed at fixed values of the drain voltage V.sub.D and the write time tp. FIG. 2C illustrates a relationship between logarithmic values of the write time tp and a change .DELTA.V.sub.TH of the threshold voltage when the data write is performed with a parameter of the drain voltage V.sub.D, while fixing the control gate voltage V.sub.G. In the figure, a curve 11 represents the relationship when the voltage V.sub.D is large and the curve 12 represents the same when the V.sub.D is small. As shown in FIGS. 2B and 2C, the higher the control gate voltage V.sub.G, the shorter the write time tp. When the write time tp is relatively long, a change .DELTA.V.sub.TH of the threshold voltage is independent of the drain voltage V.sub.D. When the time tp is relatively short, a short time is needed taken for obtaining a given amount of the change .DELTA.V.sub.TH.
However, when the boosted voltage is applied to the row line, a special boosted voltage applying means is necessary for decreasing the output current of the boosting circuit.